1. Field of the Invention
The present invention relates to a semiconductor storage device and a pseudo SRAM, in particular, a semiconductor storage device and a pseudo SRAM provided with an ECC computating circuit for computing ECC (error correcting code) bits.
2. Description of Related Art
ECC memories supporting an ECC (error correcting code) function have been known in the art. The ECC memories can specify a portion (bit) where an error occurs to correct the error as well as simply detects a memory error. Information used for ECC check is hereinafter referred to as “ECC bits”.
The number of ECC bits is determined based on a Hamming code. When a data bus width is N bits, the number of bits is determined by calculating the base 2 logarithm with respect to N and adding the calculation result to 2. For example, assuming that the data bus width is 64 bits, 8 bits are required as ECC bits. As a result, assuming that the data bus width is 64 bits, the ECC bits of 32 bits (=8×4) in total are necessary for 256-bit data.
Japanese Unexamined Patent Publication No. 11-102326 discloses how to reduce the number of ECC bits. According to a semiconductor storage device disclosed in Japanese Unexamined Patent Publication No. 11-102326, ECC bits are calculated using all the data subjected to burst transmission. For example, when the data bus width is 64 bits, and the burst length is 4, one ECC bit value is calculated for 256-bit data. In this case, the requisite number of ECC bits is 9 bits. That is, the number of ECC bits can be kept low.
The above related art involves the following problems. That is, only data less than 256 bits (for example, 1 byte) is written although the number of data bits necessary for calculating the ECC bits is, for example, 256 bits, the ECC bits cannot be calculated. The same problem arises in such a case that burst write is executed but the burst-transmission data is masked.